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About the Role
This role sits at the intersection of the AiWACS radar signal processor and the PAiREGRINE onboard compute stack. You will develop the FPGA-based low-latency preprocessing pipeline that fuses radar, EO/IR, thermal, and RF data for real-time edge inference on the drone.
Key Responsibilities
• Develop FPGA firmware (VHDL/Verilog) for real-time radar signal processing (pulse compression, beamforming, CFAR detection)
• Build low-latency data pipelines from sensor inputs (ADC, camera, RF receiver) through FPGA to ARM/Jetson compute modules
• Implement real-time AES-256 encrypted datalink telemetry (FHSS, MANET/MIMO radio integration)
• Develop and optimise embedded C/C++ firmware for flight computer and mission processor
• Integrate with ROS-based autonomy stack for UAV sensor fusion and mission execution
• Support hardware-in-the-loop (HIL) testing and radar receiver characterisation
Required Qualifications
• BSc/MSc in Electrical Engineering, Embedded Systems, or Computer Engineering
• 3+ years FPGA design (Xilinx Zynq / Ultrascale, Intel Arria / Stratix)
• Proficient in VHDL or Verilog; experience with Vivado/Quartus toolchains
• Embedded C/C++ on bare-metal or RTOS (FreeRTOS, VxWorks, or similar)
• Familiarity with high-speed interfaces: PCIe, Ethernet, JESD204B, LVDS
Bonus / Differentiators
• Experience with radar signal processing in FPGA (SAR, FMCW, pulse-Doppler)
• ROS/ROS2 integration experience for drone payloads
• Familiarity with MIL-STD-1553, ARINC 429, or DO-178C development processes
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