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About the Role
You will be the core technical driver of F.A.S.T. 's AiWACS radar programme — the world's first all-digital S-Band AESA radar chipset developed in house at AUS and now being miniaturised to chipset level for airborne deployment. This role owns the RF architecture from antenna through to signal chain.
Key Responsibilities
• Lead end-to-end RF system architecture for the S-Band AESA phased-array radar (16-channel, 600 MHz chirp bandwidth, 25 cm range resolution)
• Design and characterise high-dynamic-range transceiver chains (70 dB dynamic range target)
• Develop stretch-processing waveform algorithms for high-resolution range profiling with lower ADC sampling rates
• Drive digital beamforming and STAP algorithm development for moving-target detection
• Collaborate with RFIC designers on chipset tape-out readiness and wafer characterisation
• Interface with UAV integration teams to meet SWaP constraints (<100 kg, airborne AWACS UAV)
• Support IP and patent filing for novel radar architectures
Required Qualifications
• MSc or PhD in Electrical Engineering, RF Engineering, or related field
• 5+ years hands-on radar or RF systems design experience
• Proficiency in FMCW/OFDM radar waveform design and range-Doppler processing
• Experience with phased array systems, digital beamforming, or AESA architectures
• Proficient in MATLAB, Python for signal processing and simulation
• Experience with S-Band or L-Band radar (military / ATC / weather applications)
• Background in RFIC design or tape-out exposure (TSMC, GlobalFoundries processes)
• Publications or patents in radar miniaturisation or phased array design
• UAE security clearance eligibility preferred
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