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Experience : 5 to 12 years
Key Responsibilities
• Define and develop SoC / subsystem / IP verification plans aligned to architecture specifications
• Build and maintain System Verilog/UVM-based testbenches and verification environments
• Develop constrained-random and directed test scenarios and validation content
• Execute simulation and emulation-based verification to validate functionality, power, and performance
• Perform debug and root-cause analysis of RTL and testbench failures in pre silicon environment
• Analyze and drive functional, code, and assertion coverage closure
• Collaborate with architecture, RTL design, post silicon, and validation teams
• Document verification plans and participate in design/verification reviews
• Continuously improve verification methodology, infrastructure, and automation flows
• Incorporate learning from post silicon validation to enhance future verification coverage
• Good at leveraging AI across verification coding, debugging , quality sign-off requirements.
• Minimum 5 to 12 year of relevant experience in SoC/subsystem/IP level verification
• Qualifications BE or B Tech or M Tech ECE or Computer Science with 5 to 12 years front-end pre-si verification.
Work Model for this Role
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