Mixed Signal Logic Verification Engineer

Job Details:

Job Description:

A Senior/Staff VLSI Verification Engineer with 11-15 years of experience drives complex SoC/ASIC verification, focusing on UVM/System Verilog testbench architecture, Mix signal IP verification strategy, and post-silicon debug. Key responsibilities include defining verification plans, guiding junior engineers, improving verification methodologies, ensuring coverage closure, and collaborating with architects for top-level verification.

Key Responsibilities:

• Strategy & Planning: Develop, implement, and lead comprehensive verification plans for Complex Mix Signal IPs.

  
  
  

• Methodology: Design and maintain advanced test benches, scoreboards, and checkers using System Verilog and UVM.

  
  
  

• Technical Leadership: Mentor junior engineers, conduct code reviews, and drive verification closure to meet project milestones.

  
  
  

• Debug & Analysis: Perform RTL debug, gate-level simulations, and functional/code coverage analysis.

  
  
  

• Collaboration: Work with architects and design teams to identify, debug, and resolve issues, including post-silicon failures.

  
  
  

• Formal Verification: Utilize formal methods (e.g., model checking) to verify complex, hard-to-reach corner cases.

  
  
  

Qualifications:

Required Qualifications & Experience:

• Experience: 11-15 years of, or equivalent, experience in ASIC/SoC verification.

  
  
  

• Languages & Methodologies: Expert-level knowledge of System Verilog, UVM, and Verilog.

  
  
  

• Protocols: Proficiency in standard protocols like JTAG/IJTAG/CRI/APB and multi clock domain Mix signal designs.

  
  
  

• Tools: Hands-on experience with industry-standard EDA tools (Synopsys VCS, Cadence Xcelium/JasperGold, Mentor Questa).

  
  
  

• Scripting: Strong scripting skills (Python, Perl, Tcl) for testbench automation.

  
  
  

• Education: B.E/B.Tech or M.E/M.Tech/MS in Electronics/VLSI Engineering.

  
  
  

• Domain Knowledge: Expertise Mix signal Sensor IP verification.

  
  
  

Skills:

• IP test plan development.

  
  
  

• Constraint-random test generation.

  
  
  

• Strong debugging capabilities and RCA (Root Cause Analysis).

  
  
  

• Ability to work on complex, Mix signal designs.

  
  
  

Job Type:Experienced Hire

Shift:Shift 1 (India)

Primary Location: India, Bangalore

Additional Locations:



Business group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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