Staff SoC Boot Verification Engineer

About Analog Devices

Analog Devices, Inc. (NASDAQ:ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more atwww.analog.com and onLinkedIn andTwitter (X).

We are looking for an experienced SoC Boot Verification Engineer to own pre-silicon verification of SoC boot flows—from supply ramp up to power-on reset through secure boot, ROM execution, and transition to second-stage loaders. You will ensure first-time-right bring-up across diverse boot media and configurations by defining verification strategies, architecting robust environments, and driving sign-off for boot correctness, robustness, security, and performance at the SoC level.

What You Will Do

• Boot Verification:
  • Own SoC boot verification across cold/warm boot/resets, strap/fuse/OTP configurations, boot mode selection, and firmware/OS hand-off.
  • Define coverage goals and sign-off criteria.
  • Verify authentication/encryption behavior, key provisioning interfaces, and failure/resilience paths.
  • Regression stability, MTTR on boot failures, and timely closure of security-sensitive defects.
• Boot Media & Interfaces:
  • Develop VIP/BFMs and test scenarios for QSPI/NOR/NAND, eMMC/SD, USB/UART/JTAG, PCIe or network boot.
  • Validate timeouts, retries, and error escalation.
  • Verify Analog Supply Ramp up, Analog Blocks & POR sequencing, clock/PLL enablement, power islands and retention, and their interaction with boot ROM.
• Environment & Methodology:
  • Architect reusable UVM SystemVerilog environments, scoreboards, monitors, coverage models, and assertions.
  • Drive constrained-random plus directed testing for corner cases.
  • Plan and run power aware gate-level simulations (SDF) for boot timing/CDC/RDC critical paths.
• HW/SW Co-verification:
  • Collaborate with security/firmware and bring-up teams to validate second-stage loaders, bootloader APIs, patch flows, and secure update paths.
  • Mentor engineers, review test plans, and drive methodology improvements across DV teams and programs.

Minimum Qualifications

• Education: B.Tech/M.Tech in EE/CE or related field.
• Experience: 8–14 years in SoC/DV with substantial boot/ROM/secure boot work; end-to-end ownership of complex subsystems. Proven leadership of SoC boot verification and cross-functional delivery at scale.
• Technical Expertise:
  • Strong UVM/SystemVerilog, assertions, coverage-driven verification; regression management and debug at RTL/gate.
  • Good understanding of reset/clock/power and mixed-signal elements at chip-top.
  • Python/Tcl for stimulus, log parsing, coverage analytics; CI (Jenkins), source control (Git/Perforce).

Behavioral & Collaboration Expectations

• Clear communication with architecture, RTL, security, and firmware teams.
• Crisp bug reporting and issue reproduction; data-driven closure and risk management.

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