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General Summary:
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.
Minimum Qualifications:
Job Summary
We are seeking an experienced STA Engineer (6-9 years) to drive block, subsystem timing closure on complex designs at advanced technology nodes. The role requires strong hands‑on expertise in timing analysis, constraints, power optimization, and aging signoff for large‑scale designs.
Key Responsibilities
Drive block‑level and subsystem‑level STA closure for large designs (≥10M instance count), and contribute to full‑chip STA signoff.
Perform end‑to‑end STA from post‑synthesis to signoff across latest technology nodes.
Define, validate, and maintain timing constraints including clocks, IO delays, generated clocks, exceptions (false paths, multi‑cycle paths), and case analysis.
Execute MMMC timing analysis across multiple modes, PVT, and parasitic corners.
Analyze and debug setup, hold, recovery, removal, clock gating, min period, and pulse width violations.
Drive timing closure by collaborating with PD, synthesis, clocking, power, and ECO teams.
Perform and review crosstalk/noise analysis, parasitic quality checks, and constraint sanity checks.
Support timing ECOs, re‑analysis, and final tapeout signoff.
Develop and maintain TCL automation for STA flows, checks, and reporting.
Provide clear timing signoff status, risk assessment, and recommendations to cross‑functional teams.
Required Skills & Qualifications
7-9 years of hands‑on experience in Static Timing Analysis.
Proven experience in block and subsystem STA closure for large designs (≥10M instances).
Strong expertise with PrimeTime and/or Tempus.
Deep understanding of:
Timing constraints and constraint debugging
MMMC concepts, PVT scaling, CRPR/CPPR
OCV/AOCV/POCV methodologies
Working knowledge of power optimization techniques, including:
Timing‑power tradeoffs
Power‑aware timing analysis
Coordination with power intent and low‑power flows
Solid understanding of aging concepts and their impact on timing (BTI/HCI‑aware signoff, derates).
Experience with hierarchical STA, ILM/ETM based flows.
Strong TCL scripting capability for automation and analysis.
Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
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If you would like more information about this role, please contact Qualcomm Careers.
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