Submitting more applications increases your chances of landing a job.

Here’s how busy the average job seeker was last month:

Opportunities viewed

Applications submitted

Keep exploring and applying to maximize your chances!

Looking for employers with a proven track record of hiring women?

Click here to explore opportunities now!
We Value Your Feedback

You are invited to participate in a survey designed to help researchers understand how best to match workers to the types of jobs they are searching for

Would You Be Likely to Participate?

If selected, we will contact you via email with further instructions and details about your participation.

You will receive a $7 payout for answering the survey.


User unblocked successfully
https://bayt.page.link/4qSRKa26sZK1ycty9
Back to the job results

Senior Hardware Verification Engineer

19 days ago 2026/08/24
Other Business Support Services
Create a job alert for similar positions
Job alert turned off. You won’t receive updates for this search anymore.

Job description

The Senior ASIC Hardware Verification Engineer is responsible for the end-to-end functional verification of complex digital designs (IP, Subsystem, or SoC). You will architect advanced UVM-based testbenches, define exhaustive verification plans, and lead the "coverage closure" process to ensure the design meets all architectural specifications before tape-out.


Key Responsibilities
  • Verification Strategy: Define and document the verification plan (vPlan), including test scenarios, checkers, and functional coverage models.


  • Testbench Architecture: Architect and implement scalable, reusable verification environments using SystemVerilog and UVM.


  • Advanced Stimulus: Develop constrained-random stimulus and directed tests to stress-test corner cases of the micro-architecture.


  • Debugging: Root-cause complex hardware failures by analyzing waveforms (VPD/FSDB) and collaborating with RTL designers.


  • Coverage Closure: Drive functional and code coverage to 100%, utilizing exclusions and refined stimulus to reach uncovered logic.


  • Performance & Power: Verify throughput, latency, and power-aware (UPF/CPF) features of the silicon.


  • Mixed-Methods: Integrate Formal Verification (JasperGold/VC Formal) for control logic and Hardware Emulation (Palladium/Zebu) for long-latency system tests.


  • Mentorship: Provide technical leadership to junior engineers and perform code reviews for testbench components.



More information about NXP in India...


#LI-2734
This job post has been translated by AI and may contain minor differences or errors.

You’ve reached the maximum limit of 15 job alerts. To create a new alert, please delete an existing one first.
Job alert created for this search. You’ll receive updates when new jobs match.
Are you sure you want to unapply?

You'll no longer be considered for this role and your application will be removed from the employer's inbox.