Hardware Verification Engineer

Introduction

At IBM Infrastructure & Technology, we design and operate the systems that keep the world running. From high-resiliency mainframes and hybrid cloud platforms to networking, automation, and site reliability. Our teams ensure the performance, security, and scalability that clients and industries depend on every day. Working in Infrastructure & Technology means tackling complex challenges with curiosity and collaboration. You'll work with diverse technologies and colleagues worldwide to deliver resilient, future-ready solutions that power innovation. With continuous learning, career growth, and a supportive culture, IBM provides the opportunities to build expertise and shape the infrastructure that drives progress.

Your role and responsibilities

As a ASIC Functional verification Lead, you will be working on IBM SOC or ASICs used in IBM servers and for other customers.
Leading the development of the verification environment, testbenches and writing testcases.
Develop skills in IBM Functional verification tools and methodologies.
Work with design as well as other key stakeholders in debugging and fixing logic design issues and deliver a quality design.
Work with development team to ensure coverage criteria is met.
Lead a young team by defining driving and delivering the best quality chips.

Required education
Bachelor's Degree

Required technical and professional expertise

15 + years of experience in Functional Verification of processors or ASICs.

Minimum 15+ years of experience in any of the followingExperience with 3rd party IP blocks: DDR/Ethernet/PCIe/USB, NAND, or AXI.

Self-Starter, ready to move quickly to keep the design moving forward.

IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc.AXI/AHB/ACE/ACE-lite fabric verification or any other SoC fabric verification.

Gate level simulation and emulation.Track record in leading team.

Clock domain crossing and reset domain crossing verification.

Knowledge of functional verification methodology - UVM/OVM/System Verilog/SystemC/.Knowledge of HDLs (Verilog, VHDL).

Developed test-plans and test strategies for IP/unit/block level verification.Good object-oriented programming skills in C/C++, scripting languages like Python/Perl.

Worked on multiple levels of verification (unit/element/sub-system/system level).

Development experience on Linux/Unix environments, GIT repositories and good understanding of Continuous Integration and DevOps workflow.

Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails

Preferred technical and professional experience

Stress testing and ability to identify corner case scenarios. Knowledge of high-speed SERDES and PHY Verification. Good understanding of computer system architecture and microarchitecture. Knowledge in IP Integration and SoC level verification. Exposure to automation.

Years of Experience:
15-25