Static Timing Analysis Engineer

Introduction

At IBM Infrastructure & Technology, we design and operate the systems that keep the world running. From high-resiliency mainframes and hybrid cloud platforms to networking, automation, and site reliability. Our teams ensure the performance, security, and scalability that clients and industries depend on every day. Working in Infrastructure & Technology means tackling complex challenges with curiosity and collaboration. You'll work with diverse technologies and colleagues worldwide to deliver resilient, future-ready solutions that power innovation. With continuous learning, career growth, and a supportive culture, IBM provides the opportunities to build expertise and shape the infrastructure that drives progress.
The physical design team is responsible for designing high-performance microprocessor blocks for IBM Power and z mainframe servers.

Your role and responsibilities

1. STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs.
2. Timing analysis, validation and debug across multiple PVT conditions using Tempus.
3. Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.
4. Hands-on experience with STA tools - Tempus
5. In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling

Required education
Bachelor's Degree

Preferred education
Master's Degree

Required technical and professional expertise
Solid experience in place & route flow (placement guidelines, clock-tree synthesis, routing, timing optimizations).Experience on hierarchical designs and/or Low Power implementation is an advantage.Experience on Synthesis, interfacing with RTL and implementationExperience on Floorplan design, including placement of hard macros, congestion reduction techniques.Experience on Static Timing Analysis related activities , parasitic extractions, sign-off requirements).Knowledge of Physical Verification (DRC/LVS/DFM, chip finishing) is an added advantage

Preferred technical and professional experience

DDR and PCIe timing closure

Years of Experience:
7-12