Principal Engineer, DFT

Company:Qualcomm India Private Limited
Job Area:Engineering Group, Engineering Group > Hardware Engineering

General Summary:

Job Description

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.

• Additional Job Description
  

  Qualcomm’s Global CAD Organization is seeking a MBIST and ATPG CAD/Methodology Development Engineer to develop DFT methodologies for Qualcomm products in next-generation semiconductor process nodes. In this role, you will be part of a global technical team collaborating across SoC Design, DFT, Product & Test, Diagnostics, and EDA tool partners to deliver world-class DFT solutions.

  
  
  

  
  Key Responsibilities

  
  
  

  • Design, develop, and deploy MBIST flow capabilities within the DFT CAD team, working closely with worldwide DFT teams, Memory IP design groups, EDA vendors, Test Engineering, and Diagnostics teams.

    
    
    

  • Innovate and implement new MBIST methodologies for advanced process nodes, emerging SRAM architectures, 3-D chip designs.

    
    
    

  • Evaluate new tools and features, design experiments (DoEs), and partner with EDA vendors to enhance MBIST capabilities.

    
    
    

  • Create optimized methodologies to reduce MBIST implementation effort, improve test quality, lower test cost, shorten DFT cycle time, and accelerate pattern simulation runtimes.

    
    
    

  • Deliver accurate collaterals to support memory repair, diagnostics, and failure analysis.

    
    
    

  NOTE: This is DFT methodology development role and is NOT a DFT design implementation/execution role.

  
  
  
  
  

  Qualifications/Experience

  
  
  

  • BE/B.Tech, ME/MTech/MS in Electrical/Electronics/VLSI/Computer Science Engineering

    
    
    

  • 15+ years demonstrated experience in VLSI EDA/CAD methodology development specifically in MBIST domain

    
    
    
  
  
  

  Skills Required

  
  
  

  • Deep expertise in MBIST, ATPG including planning, insertion, verification, vector generation, memory repair, and diagnostics.

    
    
    

  • Strong hands-on experience with MBIST EDA tools (e.g., Synopsys SMS, Tessent MBIST).

    
    
    

  • Strong proficiency in scripting languages such as TCL (for EDA tools) and Python.

    
    
    

  • Solid understanding of memory architectures and BIST algorithms.

    
    
    

  • Knowledge of SoC DFT workflows, ATE requirements, and industry practices.

    
    
    

  • Familiarity with software development processes including configuration management, QA, release, and support, with strong quality focus.

    
    
    

  • Excellent collaboration skills to work effectively with global teams in a fast-paced environment.

    
    
    

  • Detail-oriented, adaptable, and a strong team player with the ability to multi-task.

    
    
    
  
  

  Keywords:

  
  
  

  MBIST, VLSI Test, Tessent BIST, SMS, SRAM Test, Memory Repair

  
  
  

Attachments

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