Layout Designer Memory

Introduction

India Systems Development Lab (ISDL) is part of IBM Systems world-wide technology development lab. Established in 1996, the Lab is headquartered in India's Silicon Valley and startup hub - Bengaluru, with a strong presence in Pune and Hyderabad. Developers at ISDL deliver technology innovations across the entire Systems portfolio - z Systems, Power / OpenPOWER Systems and Storage. The team here works across the entire stack from processor design, firmware, operating system to software defined storage. The lab also focuses on innovations, thanks to the creative energies of the teams. The lab has contributed over 400+ patents in cutting edge technologies and inventions so far.

While computing veers towards cognitive, cloud, mobile, social, and security, the lab has significantly contributed to not just new products focused in these areas, but has also ushered in new development models such as Agile, Design Thinking and DevOps. The engineer hired will be working on SRAM memory layouts for our projects working directly with designers from US/Germany.

Your role and responsibilities

This role does design and layout of complex VLSI (very large scale integration) circuits using graphic editing tools in cutting edge technological nodes. A major portion of the job is in creation of new physical design data from concepts, partial schematics or a working knowledge of overall requirements. Responsibilities include checking the design integrity with respect to semiconductor ground rules and the logical function of the circuit. Symbolic circuit data (schematics) are converted to physical shapes which represent the semiconductor process. The role ranges from manual shapes and checking tool manipulations to extended team coordination and methodology creation. The employee guides functional objectives or technologies. The designer should be able to automate

Required education
Bachelor's Degree

Preferred education
Master's Degree

Required technical and professional expertise

5-7 Years of relevant experience in SRAM layouts for lower technology nodes like 5nm and below.

Experience in developing layouts for memories like Caches, CAMs, Register files, multiport register Files, Compilers etc

1)Should be in a position to work hands on layouts

2) Should be able to work on projects across multi-discipline, multi-cultural and multi-site environments

4) Strong fundamental knowledge in semiconductor device physics, layout principles, IC reliability and failure mechanisms

5) Good problem-solving skills are essential where problems are analysed upfront, identifying gaps, and providing optimum solutions

6) Work closely with required global teams to ensure the success of the whole project

Preferred technical and professional experience

Coding and AI skills are a plus

Years of Experience:
5-7