Hardware Verification Engineer (RTL)

Project description We are looking for an HW verification engineer who will be responsible for RTL verification, developing SV/UVM testbenches at Top/Sub-system/Block-levels. Also, responsible for driving test plan and test spec development and execution, generating documents, such as user guide, test plan, test spec, test report, etc. Responsibilities Develop and execute verification environments using SystemVerilog and UVM for FPGA/ASIC designs. Verify and validate protocols such as Ethernet, PCIe, SPI, I2C, and USB across different use cases. Perform hardware validation and testing using lab equipment (logic analyzers, traffic generators, etc.). Debug and resolve issues at the device and board level, ensuring design reliability and coverage closure. Collaborate with design and hardware teams to integrate, test, and optimize FPGA-based solutions on Xilinx platforms. Skills Must have 5-10y exp Strong experience in SystemVerilog and UVM-based verification Hands-on experience in protocol verification (Ethernet, PCIe, SPI, I2C, USB) Experience in FPGA verification and Xilinx tools/technologies Strong hardware debugging skills at the device and board level Experience in scripting (Python/Perl/TCL) for automation and test development Nice to have Good problem-solving and communication skills Other Languages English: B2 Upper Intermediate Seniority Senior